About Me

I am a graduate student at Penn State CSE, working with Aasheesh Kolli. I also collaborate with Irina Calciu at VMware Research.

I was a research intern in Summer 2020 at VMware Research and Summer 2019 at Facebook.

Note: I am looking for full-time opportunities (expected MS graduation: May 2021) in the broad area of datacenter scale systems, including: operating systems, memory systems, microservices, and cloud computing.

Links:
Curriculum Vitae (March 2020)
LinkedIn
Github

News

• 11/20: Paper accepted at ASPLOS’21
• 05/20: Summer Research Internship @ VMware Research Group
• 05/19: Summer Research Internship @ Facebook, Menlo Park (AI HW/SW Codesign Team)
• 02/19: Presented “Rethinking Resource Disaggregation” @ Young Architect Workshop, HPCA’19
• 08/18: Started Grad School @ Penn State CSE

Publications

• [ASPLOS 2021] Rethinking Software Runtimes for Disaggregated Memory
  Irina Calciu, M. Talha Imran, Ivan Puddu, Sanidhya Kashyap, Hasan Al Maruf, Onur Mutlu, Aasheesh Kolli


• [YArch @ HPCA 2019] Rethinking Resource Disaggregation
  M. Talha Imran, Aasheesh Kolli.


• [ROBIO 2015] Designing of motions for humanoid goal keeper robots
  Idrees Hussain, M. Talha Imran, Abdul Haseeb Ayub, Shams Azeem, Maham Tanveer, Fahad Islam, and Yasar Ayaz

Research

Serverless

I am exploring serverless scheduling approaches from cloud providers’ perspective to reduce costs (e.g. resource oversubscription) using our serverless testbed comprising open-source components including cluster manager, serverless frameworks, cloud infrastructure services, and distributed load generator.

Disaggregated Systems

We are developing a user-space remote memory system based on RDMA, Linux user-space page faults, and io_uring to improve portability and ease-of-adoption while maintaining performance. We also characterized full-scale real-world applications to glean requirements for a transparent fine-grained remote memory system.

HW Accelerator Programmability

We devised an analysis methodology to characterize machine learning hardware accelerators’ software-backend development costs arising from hardware design complexity.

Background

I am a technology enthusiast – intrigued by the utility, organization and implementation of everything with a digital heartbeat.

I have long been interested in bridging the hardware and software worlds. This has led me to pursue Robotics in undergrad, followed by developing low-level software tools for embedded systems at Siemens (formerly Mentor Graphics), leading up to my current endeavors with Computer Systems and Architecture. I am intrigued by complexity of datacenter scale systems and how recent computing paradigms (like serverless) and technologies (like RDMA) can improve efficiency and resource utilization.

Food, travel, world affairs, movies, and sometimes cars devour my attention as I attempt to attain some balance with lighter side of life. (more stuff here)

Contact

Email: timran -AT- psu -DOT- edu 

Address:
W209 Westgate Building,
University Park, PA, 16802